// $Module: reg_cmdq $
// $RegisterBank Version: V 1.0.00 $
// $Author: Test 123 $
// $Date: Sun, 05 Dec 2021 04:15:49 PM $
//

//GEN REG ADDR/OFFSET/MASK
#define  CMDQ_INT_EVENT  0x0
#define  CMDQ_INT_EN  0x4
#define  CMDQ_DMA_ADDR  0x8
#define  CMDQ_DMA_CNT  0x10
#define  CMDQ_DMA_CONFIG  0x14
#define  CMDQ_AXI_CONFIG  0x18
#define  CMDQ_JOB_CTL  0x1c
#define  CMDQ_APB_PARA  0x24
#define  CMDQ_DEBUG_BUS0  0x28
#define  CMDQ_DEBUG_BUS1  0x2c
#define  CMDQ_DEBUG_BUS2  0x30
#define  CMDQ_DEBUG_BUS3  0x34
#define  CMDQ_DEBUG_BUS_SEL  0x38
#define  CMDQ_DUMMY  0x3c
#define  CMDQ_TASK_DONE_STS  0x40
#define  CMDQ_DMA_ADDR_TSK0  0x80
#define  CMDQ_DMA_CNT_TSK0  0x88
#define  CMDQ_DMA_ADDR_TSK1  0x90
#define  CMDQ_DMA_CNT_TSK1  0x98
#define  CMDQ_DMA_ADDR_TSK2  0xa0
#define  CMDQ_DMA_CNT_TSK2  0xa8
#define  CMDQ_DMA_ADDR_TSK3  0xb0
#define  CMDQ_DMA_CNT_TSK3  0xb8
#define  CMDQ_DMA_ADDR_TSK4  0xc0
#define  CMDQ_DMA_CNT_TSK4  0xc8
#define  CMDQ_DMA_ADDR_TSK5  0xd0
#define  CMDQ_DMA_CNT_TSK5  0xd8
#define  CMDQ_DMA_ADDR_TSK6  0xe0
#define  CMDQ_DMA_CNT_TSK6  0xe8
#define  CMDQ_DMA_ADDR_TSK7  0xf0
#define  CMDQ_DMA_CNT_TSK7  0xf8
#define  CMDQ_REG_CMDQ_INT   0x0
#define  CMDQ_REG_CMDQ_INT_OFFSET 0
#define  CMDQ_REG_CMDQ_INT_MASK   0x1
#define  CMDQ_REG_CMDQ_INT_BITS   0x1
#define  CMDQ_REG_CMDQ_END   0x0
#define  CMDQ_REG_CMDQ_END_OFFSET 1
#define  CMDQ_REG_CMDQ_END_MASK   0x2
#define  CMDQ_REG_CMDQ_END_BITS   0x1
#define  CMDQ_REG_CMDQ_WAIT   0x0
#define  CMDQ_REG_CMDQ_WAIT_OFFSET 2
#define  CMDQ_REG_CMDQ_WAIT_MASK   0x4
#define  CMDQ_REG_CMDQ_WAIT_BITS   0x1
#define  CMDQ_REG_ISP_PSLVERR   0x0
#define  CMDQ_REG_ISP_PSLVERR_OFFSET 3
#define  CMDQ_REG_ISP_PSLVERR_MASK   0x8
#define  CMDQ_REG_ISP_PSLVERR_BITS   0x1
#define  CMDQ_REG_TASK_END   0x0
#define  CMDQ_REG_TASK_END_OFFSET 4
#define  CMDQ_REG_TASK_END_MASK   0x10
#define  CMDQ_REG_TASK_END_BITS   0x1
#define  CMDQ_REG_CMDQ_INT_EN   0x4
#define  CMDQ_REG_CMDQ_INT_EN_OFFSET 0
#define  CMDQ_REG_CMDQ_INT_EN_MASK   0x1
#define  CMDQ_REG_CMDQ_INT_EN_BITS   0x1
#define  CMDQ_REG_CMDQ_END_EN   0x4
#define  CMDQ_REG_CMDQ_END_EN_OFFSET 1
#define  CMDQ_REG_CMDQ_END_EN_MASK   0x2
#define  CMDQ_REG_CMDQ_END_EN_BITS   0x1
#define  CMDQ_REG_CMDQ_WAIT_EN   0x4
#define  CMDQ_REG_CMDQ_WAIT_EN_OFFSET 2
#define  CMDQ_REG_CMDQ_WAIT_EN_MASK   0x4
#define  CMDQ_REG_CMDQ_WAIT_EN_BITS   0x1
#define  CMDQ_REG_ISP_PSLVERR_EN   0x4
#define  CMDQ_REG_ISP_PSLVERR_EN_OFFSET 3
#define  CMDQ_REG_ISP_PSLVERR_EN_MASK   0x8
#define  CMDQ_REG_ISP_PSLVERR_EN_BITS   0x1
#define  CMDQ_REG_TASK_END_EN   0x4
#define  CMDQ_REG_TASK_END_EN_OFFSET 4
#define  CMDQ_REG_TASK_END_EN_MASK   0x10
#define  CMDQ_REG_TASK_END_EN_BITS   0x1
#define  CMDQ_REG_DMA_ADDR   0x8
#define  CMDQ_REG_DMA_ADDR_OFFSET 0
#define  CMDQ_REG_DMA_ADDR_MASK   0xffffffffff
#define  CMDQ_REG_DMA_ADDR_BITS   0x28
#define  CMDQ_REG_DMA_CNT   0x10
#define  CMDQ_REG_DMA_CNT_OFFSET 0
#define  CMDQ_REG_DMA_CNT_MASK   0xffffffff
#define  CMDQ_REG_DMA_CNT_BITS   0x20
#define  CMDQ_REG_DMA_RSV   0x14
#define  CMDQ_REG_DMA_RSV_OFFSET 0
#define  CMDQ_REG_DMA_RSV_MASK   0x1
#define  CMDQ_REG_DMA_RSV_BITS   0x1
#define  CMDQ_REG_ADMA_EN   0x14
#define  CMDQ_REG_ADMA_EN_OFFSET 1
#define  CMDQ_REG_ADMA_EN_MASK   0x2
#define  CMDQ_REG_ADMA_EN_BITS   0x1
#define  CMDQ_REG_TASK_EN   0x14
#define  CMDQ_REG_TASK_EN_OFFSET 2
#define  CMDQ_REG_TASK_EN_MASK   0x4
#define  CMDQ_REG_TASK_EN_BITS   0x1
#define  CMDQ_REG_MAX_BURST_LEN   0x18
#define  CMDQ_REG_MAX_BURST_LEN_OFFSET 0
#define  CMDQ_REG_MAX_BURST_LEN_MASK   0xff
#define  CMDQ_REG_MAX_BURST_LEN_BITS   0x8
#define  CMDQ_REG_OT_ENABLE   0x18
#define  CMDQ_REG_OT_ENABLE_OFFSET 8
#define  CMDQ_REG_OT_ENABLE_MASK   0x100
#define  CMDQ_REG_OT_ENABLE_BITS   0x1
#define  CMDQ_REG_SW_OVERWRITE   0x18
#define  CMDQ_REG_SW_OVERWRITE_OFFSET 9
#define  CMDQ_REG_SW_OVERWRITE_MASK   0x200
#define  CMDQ_REG_SW_OVERWRITE_BITS   0x1
#define  CMDQ_REG_JOB_START   0x1c
#define  CMDQ_REG_JOB_START_OFFSET 0
#define  CMDQ_REG_JOB_START_MASK   0x1
#define  CMDQ_REG_JOB_START_BITS   0x1
#define  CMDQ_REG_CMD_RESTART   0x1c
#define  CMDQ_REG_CMD_RESTART_OFFSET 1
#define  CMDQ_REG_CMD_RESTART_MASK   0x2
#define  CMDQ_REG_CMD_RESTART_BITS   0x1
#define  CMDQ_REG_RESTART_HW_MOD   0x1c
#define  CMDQ_REG_RESTART_HW_MOD_OFFSET 2
#define  CMDQ_REG_RESTART_HW_MOD_MASK   0x4
#define  CMDQ_REG_RESTART_HW_MOD_BITS   0x1
#define  CMDQ_REG_CMDQ_IDLE_EN   0x1c
#define  CMDQ_REG_CMDQ_IDLE_EN_OFFSET 3
#define  CMDQ_REG_CMDQ_IDLE_EN_MASK   0x8
#define  CMDQ_REG_CMDQ_IDLE_EN_BITS   0x1
#define  CMDQ_REG_BASE_ADDR   0x24
#define  CMDQ_REG_BASE_ADDR_OFFSET 0
#define  CMDQ_REG_BASE_ADDR_MASK   0xffff
#define  CMDQ_REG_BASE_ADDR_BITS   0x10
#define  CMDQ_REG_APB_PPROT   0x24
#define  CMDQ_REG_APB_PPROT_OFFSET 16
#define  CMDQ_REG_APB_PPROT_MASK   0x70000
#define  CMDQ_REG_APB_PPROT_BITS   0x3
#define  CMDQ_REG_DEBUS0   0x28
#define  CMDQ_REG_DEBUS0_OFFSET 0
#define  CMDQ_REG_DEBUS0_MASK   0xffffffff
#define  CMDQ_REG_DEBUS0_BITS   0x20
#define  CMDQ_REG_DEBUS1   0x2c
#define  CMDQ_REG_DEBUS1_OFFSET 0
#define  CMDQ_REG_DEBUS1_MASK   0xffffffff
#define  CMDQ_REG_DEBUS1_BITS   0x20
#define  CMDQ_REG_DEBUS2   0x30
#define  CMDQ_REG_DEBUS2_OFFSET 0
#define  CMDQ_REG_DEBUS2_MASK   0xffffffff
#define  CMDQ_REG_DEBUS2_BITS   0x20
#define  CMDQ_REG_DEBUS3   0x34
#define  CMDQ_REG_DEBUS3_OFFSET 0
#define  CMDQ_REG_DEBUS3_MASK   0xffffffff
#define  CMDQ_REG_DEBUS3_BITS   0x20
#define  CMDQ_REG_DEBUS_SEL   0x38
#define  CMDQ_REG_DEBUS_SEL_OFFSET 0
#define  CMDQ_REG_DEBUS_SEL_MASK   0x3
#define  CMDQ_REG_DEBUS_SEL_BITS   0x2
#define  CMDQ_REG_DUMMY   0x3c
#define  CMDQ_REG_DUMMY_OFFSET 0
#define  CMDQ_REG_DUMMY_MASK   0xffffffff
#define  CMDQ_REG_DUMMY_BITS   0x20
#define  CMDQ_REG_TASK_DONE   0x40
#define  CMDQ_REG_TASK_DONE_OFFSET 0
#define  CMDQ_REG_TASK_DONE_MASK   0xff
#define  CMDQ_REG_TASK_DONE_BITS   0x8
#define  CMDQ_REG_DMA_ADDR_TSK0   0x80
#define  CMDQ_REG_DMA_ADDR_TSK0_OFFSET 0
#define  CMDQ_REG_DMA_ADDR_TSK0_MASK   0xffffffffff
#define  CMDQ_REG_DMA_ADDR_TSK0_BITS   0x28
#define  CMDQ_REG_DMA_CNT_TSK0   0x88
#define  CMDQ_REG_DMA_CNT_TSK0_OFFSET 0
#define  CMDQ_REG_DMA_CNT_TSK0_MASK   0xffffffff
#define  CMDQ_REG_DMA_CNT_TSK0_BITS   0x20
#define  CMDQ_REG_DMA_ADDR_TSK1   0x90
#define  CMDQ_REG_DMA_ADDR_TSK1_OFFSET 0
#define  CMDQ_REG_DMA_ADDR_TSK1_MASK   0xffffffffff
#define  CMDQ_REG_DMA_ADDR_TSK1_BITS   0x28
#define  CMDQ_REG_DMA_CNT_TSK1   0x98
#define  CMDQ_REG_DMA_CNT_TSK1_OFFSET 0
#define  CMDQ_REG_DMA_CNT_TSK1_MASK   0xffffffff
#define  CMDQ_REG_DMA_CNT_TSK1_BITS   0x20
#define  CMDQ_REG_DMA_ADDR_TSK2   0xa0
#define  CMDQ_REG_DMA_ADDR_TSK2_OFFSET 0
#define  CMDQ_REG_DMA_ADDR_TSK2_MASK   0xffffffffff
#define  CMDQ_REG_DMA_ADDR_TSK2_BITS   0x28
#define  CMDQ_REG_DMA_CNT_TSK2   0xa8
#define  CMDQ_REG_DMA_CNT_TSK2_OFFSET 0
#define  CMDQ_REG_DMA_CNT_TSK2_MASK   0xffffffff
#define  CMDQ_REG_DMA_CNT_TSK2_BITS   0x20
#define  CMDQ_REG_DMA_ADDR_TSK3   0xb0
#define  CMDQ_REG_DMA_ADDR_TSK3_OFFSET 0
#define  CMDQ_REG_DMA_ADDR_TSK3_MASK   0xffffffffff
#define  CMDQ_REG_DMA_ADDR_TSK3_BITS   0x28
#define  CMDQ_REG_DMA_CNT_TSK3   0xb8
#define  CMDQ_REG_DMA_CNT_TSK3_OFFSET 0
#define  CMDQ_REG_DMA_CNT_TSK3_MASK   0xffffffff
#define  CMDQ_REG_DMA_CNT_TSK3_BITS   0x20
#define  CMDQ_REG_DMA_ADDR_TSK4   0xc0
#define  CMDQ_REG_DMA_ADDR_TSK4_OFFSET 0
#define  CMDQ_REG_DMA_ADDR_TSK4_MASK   0xffffffffff
#define  CMDQ_REG_DMA_ADDR_TSK4_BITS   0x28
#define  CMDQ_REG_DMA_CNT_TSK4   0xc8
#define  CMDQ_REG_DMA_CNT_TSK4_OFFSET 0
#define  CMDQ_REG_DMA_CNT_TSK4_MASK   0xffffffff
#define  CMDQ_REG_DMA_CNT_TSK4_BITS   0x20
#define  CMDQ_REG_DMA_ADDR_TSK5   0xd0
#define  CMDQ_REG_DMA_ADDR_TSK5_OFFSET 0
#define  CMDQ_REG_DMA_ADDR_TSK5_MASK   0xffffffffff
#define  CMDQ_REG_DMA_ADDR_TSK5_BITS   0x28
#define  CMDQ_REG_DMA_CNT_TSK5   0xd8
#define  CMDQ_REG_DMA_CNT_TSK5_OFFSET 0
#define  CMDQ_REG_DMA_CNT_TSK5_MASK   0xffffffff
#define  CMDQ_REG_DMA_CNT_TSK5_BITS   0x20
#define  CMDQ_REG_DMA_ADDR_TSK6   0xe0
#define  CMDQ_REG_DMA_ADDR_TSK6_OFFSET 0
#define  CMDQ_REG_DMA_ADDR_TSK6_MASK   0xffffffffff
#define  CMDQ_REG_DMA_ADDR_TSK6_BITS   0x28
#define  CMDQ_REG_DMA_CNT_TSK6   0xe8
#define  CMDQ_REG_DMA_CNT_TSK6_OFFSET 0
#define  CMDQ_REG_DMA_CNT_TSK6_MASK   0xffffffff
#define  CMDQ_REG_DMA_CNT_TSK6_BITS   0x20
#define  CMDQ_REG_DMA_ADDR_TSK7   0xf0
#define  CMDQ_REG_DMA_ADDR_TSK7_OFFSET 0
#define  CMDQ_REG_DMA_ADDR_TSK7_MASK   0xffffffffff
#define  CMDQ_REG_DMA_ADDR_TSK7_BITS   0x28
#define  CMDQ_REG_DMA_CNT_TSK7   0xf8
#define  CMDQ_REG_DMA_CNT_TSK7_OFFSET 0
#define  CMDQ_REG_DMA_CNT_TSK7_MASK   0xffffffff
#define  CMDQ_REG_DMA_CNT_TSK7_BITS   0x20
